The invention relates generally to electronic memory. More particularly, the invention relates to a memory cell sensing integrator.
Computing devices require memory. The memory can include read only memory (ROM) or random access memory (RAM). Generally, memory includes memory cells that are arranged in rows and columns. The individual memory cells are accessed through the use of row select lines and column select lines, typically referred to as word lines and bit lines.
FIG. 1 shows an array of random access memory (RAM) cells 110, a row decoder 120, a column decoder 130 and associated sense amplifiers 140. The row decoder 120 selects a row of the array of RAM cells 110 through a word line (WL). The column decoder 130 selects a column of the array of the RAM cell 110 through a bit line (BL). Generally, the sense amplifiers 140 are connectable to the bit lines. The sense amplifiers 140 provide sensing of states of the memory cells.
In a resistive RAM array, the resistance of each memory cell has more than one state. The data in a memory cell can be determined by measuring a resistive state of the cell. The resistive memory cells may include magnetic layers, a fuse or anti-fuse, or any element that stores information affecting a magnitude of a nominal resistance of the memory cell.
Magnetic random access memory (MRAM) is a type of resistive memory. MRAM can include a resistive cross point array of spin dependent tunneling (SDT) junctions. Each SDT junction memory element is located at a cross point of a word line and a bit line. The magnetization of each SDT junction assumes one of two stable orientations at any given time. These two stable orientation, parallel and anti-parallel, represent logic values of xe2x80x9c0xe2x80x9d and xe2x80x9c1.xe2x80x9d The magnetization orientation affects the resistance of the SDT junction. The resistance of the SDT junction is a first value if the magnetization orientation is parallel and a second value if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction, and therefore, its logic value may be determined by sensing the resistance of the SDT junction.
Generally, sensing the resistance of an SDT junction requires sensing relatively small signals. The resistance, and therefore, the logical state of an SDT junction can be determined by applying a voltage across the SDT junction and sensing the resultant current, or by applying a current through the SDT junction and sensing the resulting voltage across the SDT junction. SDT junctions include physical characteristics that require sensing either a small amplitude sense current, or a small amplitude sense voltage.
In sensing the state of a memory cell in a memory cell array, secondary undesirable currents can be generated through unselected memory cells. Generally, all of the memory cells are coupled together through many parallel paths. Consequently, in addition to a sense current flowing through the selected memory cell, secondary or sneak path currents can flow through a number of unselected cells. These combined sneak path currents can detract and even obscure the actual sense current of the selected memory cell.
Variations in the resistance of the memory cells can make sensing the resistance of the memory cells difficult. That is, the resistance of MRAM memory cells can vary from memory cell to memory cell. A sense current resulting from a sense voltage applied to a selected memory cell will vary as greatly as the resistance of the MRAM cell. This can make sensing the resistance, and therefore, the logical state of a memory cell difficult.
Memory cell sensing can also be made difficult due to physical variations of electronic components within a memory cell sensor.
It is desirable to have an apparatus and method for sensing logical states of memory cells that can withstand resistive variations of logic states associated with the memory cells. The apparatus and method should be able to withstand physical variations of electronic components, and be operable at low signal levels. The system and method should be adaptable for used with arrays of MRAM memory cells.
The invention includes an apparatus and method for sensing logical states of memory cells that can withstand resistive variations of logic states associated with the memory cells. The system and method can withstand physical variations of electronic components, and is operable at low signal levels. The system and method are adaptable for use with MRAM.
An embodiment of the invention includes a memory cell sensor. The memory cell sensor includes an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value.
Another embodiment of the invention includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.